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主芯片和MCU

XCKU115-2FLVA1517I

XCKU115-2FLVA1517I

Kintex? UltraScale?   20nm   FPGA

產(chǎn)品特性

XCKU115  提供最佳成本/性能/功耗比,包括在中端器件、下一代收發(fā)器和低成本封裝中的最高信號(hào)處理帶寬,實(shí)現(xiàn)性能與成本效益的最佳組合。此系列適合 100G 網(wǎng)絡(luò)和數(shù)據(jù)中心應(yīng)用的包處理,以及下一代醫(yī)療成像、 8k4k 視頻和異構(gòu)無線基礎(chǔ)設(shè)施所需的 DSP 密集型處理。

特性


可編程系統(tǒng)集成
·多達(dá) 1.5M 系統(tǒng)邏輯單元,采用第 2 代 3D IC
·多芯片集成面向DSP 密集型應(yīng)用
·多個(gè)集成式 PCI Express? Gen3 核

提升的系統(tǒng)性能
·8.2 TeraMAC DSP 計(jì)算性能
·高利用率使速度提升兩個(gè)等級(jí)
·每個(gè)器件擁有高達(dá) 64 個(gè) 16G 支持背板的收發(fā)器。
·2,400Mb/s DDR4 可穩(wěn)定工作在不同 PVT 條件下

BOM 成本削減
·系統(tǒng)集成降低應(yīng)用 BOM 成本達(dá) 60%
·最慢速度極中的 12.5 Gb/s 收發(fā)器
·中間檔速率等級(jí)芯片可支持 2,400 Mb/s DDR4
·VCXO 集成可降低時(shí)鐘組件成本

總功耗削減
·較之上一代,達(dá) 40% 功耗降低
·通過 UltraScale 器件的類似于 ASIC 的時(shí)鐘實(shí)現(xiàn)精細(xì)粒度時(shí)鐘門控功能
·增強(qiáng)型系統(tǒng)邏輯單元封裝減小動(dòng)態(tài)功耗

加速設(shè)計(jì)生產(chǎn)力
·與 Virtex? UltraScale 器件引腳兼容,可擴(kuò)展性高
·與 Vivado? Design Suite 協(xié)同優(yōu)化,加快設(shè)計(jì)收斂


The Xilinx? Kintex? UltraScale? FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. The -1L devices can operate at either of two VCCINT voltages, 0.95V and 0.90V and are screened for lower maximum static power. When operated at VCCINT = 0.95V, the speed specification of a -1L device is the same as the -1 speed grade. When operated at VCCINT = 0.90V, the -1L performance and static and dynamic power is reduced. DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This data sheet, part of an overall set of documentation on the UltraScale architecture-based devices, is available on the Xilinx website at www.xilinx.com/documentation. DC Characteristics Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.19) September 22, 2020 Product Specification Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage –0.500 1.100 V VCCINT_IO(2) Internal supply voltage for the I/O banks –0.500 1.100 V VCCAUX Auxiliary supply voltage –0.500 2.000 V VCCBRAM Supply voltage for the block RAM memories –0.500 1.100 V VCCO Output drivers supply voltage for HR I/O banks –0.500 3.400 V Output drivers supply voltage for HP I/O banks –0.500 2.000 V VCCAUX_IO(3) Auxiliary supply voltage for the I/O banks –0.500 2.000 V VREF Input reference voltage –0.500 2.000 V VIN(4)(5)(6) I/O input voltage for HR I/O banks –0.400 VCCO + 0.550 V I/O input voltage for HP I/O banks –0.550 VCCO + 0.550 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(7) –0.400 2.625 V Send Feedback Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.19) September 22, 2020 www.xilinx.com Product Specification 2 VBATT Key memory battery backup supply –0.500 2.000 V IDC Available output current at the pad –20 20 mA IRMS Available RMS output current at the pad –20 20 mA GTH and GTY Transceivers VMGTAVCC Analog supply voltage for the GTH and GTY transmitter and receiver circuits –0.500 1.100 V VMGTAVTT Analog supply voltage for the GTH and GTY transmitter and receiver termination circuits –0.500 1.320 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTH and GTY transceivers –0.500 1.935 V VMGTREFCLK GTH and GTY transceiver reference clocks absolute input voltage –0.500 1.320 V VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTH and GTY transceiver columns –0.500 1.320 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.500 1.260 V IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating – 0(8) mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 10 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND – 10 mA IDCIN-PROG DC input current for receiver input pins DC coupled RX termination = Programmable – N/A(8) mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 0(8) mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 6 mA System Monitor VCCADC System Monitor supply relative to GNDADC –0.500 2.000 V VREFP System Monitor reference input relative to GNDADC –0.500 2.000 V Temperature TSTG Storage temperature (ambient) –65 150 °C TSOL Maximum soldering temperature for Pb-free component bodies(9) – 260 °C Maximum soldering temperature for Pb/Sn component bodies(9) – 220 °C
產(chǎn)品應(yīng)用

遠(yuǎn)程無線電頭端 DFE 8x8 100MHz TD-LTE 無線電單元
·100G 網(wǎng)絡(luò)接口卡,包含數(shù)據(jù)包處理器集成
·256 通道醫(yī)療超聲波圖像處理
·超高清廣播攝像機(jī)
AI 智能設(shè)備

規(guī)格
型號(hào)DataSheetDimension (mm)Description